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| (R) EMIF10-COM01 IPAD. TM EMI FILTER INCLUDING ESD PROTECTION MAIN APPLICATIONS Where EMI filtering in ESD sensitive equipment is required: Computers and printers Communication systems Mobile phones s s s DESCRIPTION The EMIF10-COM01 is a highly integrated device designed to suppress EMI / RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 flip-chip packaging means the package size is equal to the die size. That's why EMIF10-COM01 is a very small device. Additionally, this filter includes an ESD protection circuitry which prevents the protected device from destruction when subjected to ESD surges up to BENEFITS EMI symetrical (I/O) low-pass filter Very low PCB space consuming: 2 2.64 x 2.64 mm Very thin package: 0.63 mm High efficiency in ESD suppression on both input & output PINS (IEC61000-4-2 level 4). High reliability offered by monolithic integration s s s s s Flip Chip package PIN CONFIGURATION (Ball Side) 1 E D C B 01 06 2 02 07 3 03 08 4 04 09 5 05 010 COMPLIES WITH FOLLOWING STANDARD: IEC61000-4-2 level 4 15 KV (air discharge) 8 kV (contact discharge) BASIC CELL CONFIGURATION Low-pass Filter GND GND GND GND GND I6 I1 I7 I2 I8 I3 I9 I4 I10 I5 Input Output A RI/O = 200 Cinput = 45 pF ASD is a trademark of STMicroelectronics. January 2002 - Ed: 5A 1/5 EMIF10-COM01 Filtering Behavior EMIF10-COM01: Typical S21(dB) measurement on line I10/O10 0.00 dB -5.00 -10.00 -15.00 -20.00 -25.00 -30.00 -35.00 -40.00 -45.00 -50.00 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M f/Hz 1.0G 3.0G Capacitance versus reverse applied voltage C(pF) 50 40 30 20 10 0 1 2 VR(V) 3 4 5 F=1MHz Vosc=30mV Note: Spikes at high frequencies are induced by the PCB layout Analog Crosstalk: Measurements Crosstalk Behavior EMIF10-COM01: Typical A1/A2 crosstalk measurement 0.00 dB -5.00 -10.00 -15.00 -20.00 -25.00 -30.00 -35.00 -40.00 -45.00 -50.00 -55.00 -60.00 -65.00 -70.00 -75.00 -80.00 1.0M TEST BOARD 50 EMIF10 COM01 out2 in1 50 Vg 3.0M 10.0M 30.0M 100.0M f/Hz 300.0M 1.0G 3.0G Rise Time: Measurement Rise Time EMIF10-COM01 In Out Vout Square signal Generator Vc = 2.8V Vin 100k Vout Vin 2/5 EMIF10-COM01 ABSOLUTE MAXIMUM RATINGS (Tamb = 25 C) Symbol VPP Tj Top Tstg Parameter and test conditions ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharg Junction temperature Operating temperature range Storage temperature range Value 15 8 125 -40 to + 85 -55 to +150 Unit kV C C C ELECTRICAL CHARACTERISTICS (Tamb = 25C) Symbol VBR IRM VRM VCL Rd IPP RI/O Cin Parameters Breakdown voltage Leakage current @ VRM Stand-off voltage VCL VBR VRM IRM IR I Clamping voltage Dynamic impedance Peak pulse current Series resistance between Input & Output Input capacitance per line slope : 1 / R d V IPP Symbol VBR IRM Rd RI/O Cin tLH At 0V bias Vout = 2.8V IR = 1mA Test conditions Min 6 Typ 8 Max 10 500 Unit V nA VRM = 3V per line IPP = 10A, tp = 2.5s (see note 1) 180 1 200 45 Rload = 100k 220 50 25 pF ns 3/5 EMIF10-COM01 APLAC MODEL 200R in MODEL = demif10 out MODEL = demif10 Demif10 model BV = 7 IBV = 1m CJO = 25p M = 0.3333 RS = 1 VJ = 0.6 TT = 100n sub PCB grounding recommendations In order to ensure a good efficiency in terms of ESD protection and filtering behavior, we recommend to implement microvias (100 m dia.) between the GND bumps and the GND layer. GND bumps can be connected together in PCB layer 1, and in addition, if possible, use through hole vias (200 um dia.) in both sides of filter to improve contact to GND (layer). This layout will minimize the distance to the ground and thus parasitic inductances. In addition, we recommend to have GND plane wherever possible. ORDERING CODE EMIF 10 - COM 01 Version EMI Filter Nb of lines For communication 4/5 EMIF10-COM01 PACKAGE MECHANICAL DATA DIE SIZE 500 All dimensions in m 2640 s s s s s Die size: (2640 50) x (2640 50) Die height (including bumps): 650 65 Bump diameter: 315 50 Pitch: 500 50 Weight: 9.3mg 2640 MARKING 300 300 (R) diam 400 2640 FET Y WW 2640 s Y W W: Date code PACKING: EMIF10-COM01 is delivered in Tape & Reel (7 inches reel); one Tape & Reel contains 5000 dice. Note: More packing information are available in the application note AN1235: "Flip-Chip package description and recommendations for use" Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 5/5 650 |
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